Think Naturally. Think Visually. This is our vision. A complex engineering problem can be solved only by decomposing it in simpler problems. The simpler problems are then interconnected to each other, reforming the full picture of the initial problem. This decomposition in blocks can be naturally interpreted by the human brain using a visual representation.

We applied this concept in the electronic design field, by developing a tool that let the user specify and interconnect the components defined at the Register Transfer Level, using a unique, integrated and non-disruptive visual approach.

Visual IP Designer is an innovative integrated design entry tool for RTL. It support the design entry by drawing components and wiring them together and integrates the entire development flow, from the design to the verification.

Main Features:

  • Design entry using a visual approach
  • Code generation of the VHDL industry standard language
  • Import of existing VHDL modules
  • Innovative paradigm for the visual definiton of Finite State Machines
  • Visual specification of input configurations
  • Support to the verification environment
  • Cohmprensive scripting capability via TCL

Supported Platforms:

  • Microsoft Windows
  • Linux/X11
  • Solaris/X11